Superconducting Platform Technologies

 This call will consolidate Europe’s position in superconducting quantum computing through the following actions:

• Establishment of a full-stack superconducting quantum computer aiming at 1.000 physical qubits and QPU architecture based on chiplet technology. The system should feature a scalable and user-adjustable architecture, T1 coherence time above 100 us, gate fidelities (both one- and two-qubit gates, and read-out) of at least 99.9%, read-out speed below 300 ns, two-qubit gate speed below 20 ns.
• Demonstration of quantum advantage on selected industrial use cases, validated through benchmarking with best-in-class classical methods.
• Deployment of a cloud-accessible quantum system integrated with high-performance computing environments.
• Maturation of fault-tolerant quantum computing protocols, including effective quantum error correction and noise mitigation schemes.
• Delivery of a comprehensive, standardised software stack supporting system bring-up, calibration, control, benchmarking, and user access.
• Strengthened supply chains and industrial capacity in Europe for superconducting quantum technologies.

The proposal should contribute to the scale-up and practical deployment of superconducting quantum computing platforms and must address at least two of the critical technical roadblocks identified in the SRIA 2030, among which necessarily: 

• Error Correction and Fault Tolerance: the implementation of error correction and fault-tolerant quantum computing via significant improvements in gate fidelity, coherence times, and noise mitigation strategies.
• Cryogenic and Interconnect Engineering: integration with cryoelectronic and efficient signal routing at low temperatures at the scale of 1,000+ qubits, also addressing the scalability issues that prevent the implementation of an industrial-grade quantum computing platform 

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